Stackup playbook

Rigorous Stackup Planning

Templates for 2–16 layer boards with differential pair presets, impedance guardrails, and manufacturer-aligned build notes. Cross-checked with published capability matrices from Sierra Circuits, PCBWay, and Eurocircuits so you can hand fabrication notes over without surprises.

Impedance guardrailsDifferential presetsManufacturer ready

View fabrication playbook Open impedance wizard

Reference stackup templates

Layer counts align with what top manufacturers publish—copy the dielectric targets directly into your build notes.

2–16 layer coverage

2-layer build

60–65 Ω

Thickness: 0.8–1.6 mm FR-4
Copper: 1 oz outer
Differential target: 100–105 Ω
Pair spacing: 4 mil / 4 mil

Matches quick-turn capability from PCBWay and JLCPCB for hobby-to-production spins.

4-layer build

50–55 Ω (surface)

Thickness: 1.6 mm FR-4
Copper: 1 oz outer / 0.5 oz inner
Differential target: 90–95 Ω
Pair spacing: 4 mil / 6 mil

Sierra Circuits and Eurocircuits publish the same impedance guardrail for DDR and PCIe Gen3 traces.

6-layer build

50 Ω stripline

Thickness: 1.6 mm FR-4 or low-loss
Copper: 1 oz outer / 0.5 oz inner
Differential target: 85–90 Ω
Pair spacing: 5 mil / 7 mil

Pairs reference dual ground planes; keep dielectric 8–10 mil between signal and plane.

8-layer build

48–55 Ω (mix)

Thickness: 2.0 mm FR-4 hybrid
Copper: 1 oz outer / 0.5 oz inner
Differential target: 85 Ω (PCIe / USB4)
Pair spacing: 5 mil / 8 mil

Stackup mirrors fabricator templates from Advanced Circuits for production automotive builds.

10-layer build

45–50 Ω stripline

Thickness: 2.0–2.4 mm FR-4
Copper: 1 oz outer / 0.5 oz inner with heavy power plane
Differential target: 80–85 Ω
Pair spacing: 6 mil / 8 mil

Great for wide PDN planes plus dual differential highways; impedance locked within ±7 Ω.

12-layer build

45 Ω

Thickness: 2.4 mm low-loss FR-4
Copper: 1 oz outer / 0.5 oz inner + 2 oz power cores
Differential target: 80 Ω
Pair spacing: 6 mil / 10 mil

Derived from Sierra Circuits HDI book—add resin-filled vias for tight skew budgets.

14-layer build

42–45 Ω

Thickness: 2.6 mm hybrid (Megtron + FR-4)
Copper: 1 oz outer / 0.5 oz inner
Differential target: 76–80 Ω
Pair spacing: 7 mil / 10 mil

Use low-loss cores for high-speed layers while dedicating thick copper planes to power.

16-layer build

40–42 Ω

Thickness: 3.0 mm hybrid low-loss
Copper: 1 oz outer / 0.5 oz inner + 2 oz power
Differential target: 70–76 Ω
Pair spacing: 8 mil / 12 mil

Reference builds from TTM and Sanmina for complex compute modules with strict skew budgets.

Guardrails from top manufacturers

Summaries pulled from capability matrices and impedance tables published by Sierra Circuits, PCBWay, and Eurocircuits.

Sierra Circuits

IPC-4101 / 4103 compliant HDI builds with 85/100 Ω guardrails

Keep plane-to-plane spacing symmetrical and favor dual L2/L(N-1) reference planes for every diff pair layer.

PCBWay

Cost-optimized FR-4 with laser drilled microvias

Stay within 4/4 mil track/space unless you engage their advanced line; differential skew <3 ps is achievable with equal length constraints.

Eurocircuits

Production-proven 6–10 layer reference stackups

Follow their published dielectric tables to hold ±8 Ω tolerance without over-constraining copper weights.

Implementation checklist

Run through these steps before sending the playbook to your fabricator.

Budget at least two ground planes for every four routing layers to maintain return paths.
Lock copper weights early; impedance tables shift ~4 Ω whenever outer copper moves from 1 oz to 2 oz.
Use differential pair presets per layer: surface microstrip at 4 mil/4 mil for 100 Ω, inner stripline at 5 mil/7 mil for 90 Ω, buried stripline at 6 mil/10 mil for 85 Ω.
Push your fabricator for dielectric stack certification—top manufacturers will share exact resin systems so your simulations match the shop floor.

Dielectric tuning

Tweak thickness per layer

Dial in individual prepreg and core spans to mirror your fabricator’s stack drawing—updates flow straight into the viewer and total thickness readout.

Total thickness

0.80 mm

Thickness units

Prepreg

Between L1 & L2

Default 90 µm

Core

Between L2 & L3

Default 0.18 mm

Prepreg

Between L3 & L4

Default 90 µm

Core

Between L4 & L5

Default 0.18 mm

Prepreg

Between L5 & L6

Default 90 µm

Realistic view

Altium & KiCad realistic view

Flip between the two dominant CAD paradigms to preview how copper, dielectrics, and masks line up. Unit selections and dielectric tweaks stay in sync with the viewer for the current 6-layer template.

Altium summary

Matches the Layer Stack Manager naming used in Altium Designer with copper, dielectric, and mask blocks.

• Copper blocks inherit the same palette Altium/KiCad uses so operators immediately recognize signals.
• Layer order is locked with top at the first row; hover in the app to highlight specific layers.
• Thickness call-outs mimic what you would paste into fabrication notes for the 6-layer build.
• Current total thickness: 0.80 mm.

Top Soldermask

LPI mask

12 µm

Top Layer (L1)

Surface signal

35 µm Cu

Prepreg 2116

FR-4 prepreg

90 µm

Plane (L2)

Reference plane

18 µm Cu

Core dielectric

FR-4 core

0.18 mm

Signal (L3)

Stripline

18 µm Cu

Prepreg 2116

FR-4 prepreg

90 µm

Plane (L4)

Reference plane

18 µm Cu

Core dielectric

FR-4 core

0.18 mm

L10

Signal (L5)

Stripline

18 µm Cu

L11

Prepreg 2116

FR-4 prepreg

90 µm

L12

Bottom Layer (L6)

Reference plane

35 µm Cu

L13

Bottom Soldermask

LPI mask

12 µm

Fabrication notes

Export-ready summary

Copy or export the current stack details as plain text, Markdown, PDF, or a KiCad stackup helper—everything stays aligned with your unit selection.

Notes preview

Stackup: 6-layer (1.6 mm FR-4 or low-loss)
Copper spec: 1 oz outer / 0.5 oz inner
Targets: 50 Ω stripline single-ended / 85–90 Ω differential • Pair spacing 5 mil / 7 mil
Calculated thickness: 0.80 mm

Layer order (top ➜ bottom):
1. Top Soldermask — LPI mask (12 µm)
2. Top Layer (L1) — Surface signal (35 µm Cu)
3. Prepreg 2116 — FR-4 prepreg (90 µm)
4. Plane (L2) — Reference plane (18 µm Cu)
5. Core dielectric — FR-4 core (0.18 mm)
6. Signal (L3) — Stripline (18 µm Cu)
7. Prepreg 2116 — FR-4 prepreg (90 µm)
8. Plane (L4) — Reference plane (18 µm Cu)
9. Core dielectric — FR-4 core (0.18 mm)
10. Signal (L5) — Stripline (18 µm Cu)
11. Prepreg 2116 — FR-4 prepreg (90 µm)
12. Bottom Layer (L6) — Reference plane (35 µm Cu)
13. Bottom Soldermask — LPI mask (12 µm)

Dielectric spans:
• Between L1 & L2 — default 90 µm / current 0.090 mm
• Between L2 & L3 — default 0.18 mm / current 0.180 mm
• Between L3 & L4 — default 90 µm / current 0.090 mm
• Between L4 & L5 — default 0.18 mm / current 0.180 mm
• Between L5 & L6 — default 90 µm / current 0.090 mm

Guardrails:
• Budget at least two ground planes for every four routing layers to maintain return paths.
• Lock copper weights early; impedance tables shift ~4 Ω whenever outer copper moves from 1 oz to 2 oz.
• Use differential pair presets per layer: surface microstrip at 4 mil/4 mil for 100 Ω, inner stripline at 5 mil/7 mil for 90 Ω, buried stripline at 6 mil/10 mil for 85 Ω.
• Push your fabricator for dielectric stack certification—top manufacturers will share exact resin systems so your simulations match the shop floor.

Need richer formatting? Use the Markdown/PDF exports above or drop the KiCad stackup file into the Board Setup stack manager.